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[Other resource] ram

Description: 本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件，完全的代码在ALTERA的FPGA上已经通过仿真测试，保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ensure that available.
Platform: | Size: 2661 | Author: nick | Hits:

[VHDL-FPGA-Verilog] SYNC_FIFO

Description: its simple fifo.which is used to first in first out for vhdl source code
Platform: | Size: 1024 | Author: Viral | Hits:

[VHDL-FPGA-Verilog] simpleFIFO

Description: FIFO的VHDL程序,硬件描述语言源码-FIFO process of VHDL hardware description language source code
Platform: | Size: 137216 | Author: 陳皇仁 | Hits:

[VHDL-FPGA-Verilog] fifo89

Description: 一个先进先出缓冲器的vhdl源代码，深度是8，宽度是9位。-A FIFO CODE IN VHDL.
Platform: | Size: 1024 | Author: 巍山劲松 | Hits:

[VHDL-FPGA-Verilog] aFifo

Description: it is a vhdl source code for FIFO
Platform: | Size: 2048 | Author: Hadi | Hits:

[VHDL-FPGA-Verilog] 61i_async_fifo_v5_1_vhdl

Description: VHDL Code for FIFO+coregen v5.0
Platform: | Size: 9216 | Author: rocky | Hits:

[VHDL-FPGA-Verilog] EDA-experiments-based-on-VHDL

Description: 上传的文件包括E有关EDA实验的程序，比如FIFO，秒表，数字钟，七段数码管，状态机检测序列-The files uploaded contain some source code of EDA experiments based on VHDL, such as FIFO, digital clock, stop watch, digital tubes and sequential detector.
Platform: | Size: 4096 | Author: shi xin | Hits:

[VHDL-FPGA-Verilog] asdhbja

Description: 异步FIFO源代码 vhdl基于FPGA的设计，绝对值得一下，非常不给力的20 个字-vhdl code of asynchronous FIFo
Platform: | Size: 3072 | Author: 苏雪风 | Hits:

[VHDL-FPGA-Verilog] vhdl-Language-routine-highlights

Description: 工程中常用的VHDL控制模块，包括三态门，SDRAM，FIFO，PLL，RAM，FIlter等模块，非常实用的工程代码-Control module of VHDL is commonly used in engineering, including the tri-state gate, SDRAM, FIFO, PLL, RAM, FIlter module, very practical engineering code
Platform: | Size: 291840 | Author: shujian | Hits:

[source in ebook] FIFO

Description: FPGA内部FIFO存储器设计的vHdl源代码-FPGA internal FIFO memory design vHdl source code
Platform: | Size: 1024 | Author: 罗智勇 | Hits:

[VHDL-FPGA-Verilog] syn_fifo

Description: 同步FIFO源代码，使用Verilog编写，用户可以轻松转换成VHDL。-Synchronized FIFO source code
Platform: | Size: 1024 | Author: 王敏志 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: FIFO缓存器的设计及VHDL测试平台代码-FIFO buffer design and VHDL testbench code
Platform: | Size: 1790976 | Author: 叶宗英 | Hits:

[Communication-Mobile] xfft_v3_2_pipe_64

Description: vhdl ifft and fifo code with xilinx ip core to implement OFDM Basisband-vhdl ifft and fifo code with xilinx ip core to implement OFDM Basisband
Platform: | Size: 3118080 | Author: xy | Hits:

[VHDL-FPGA-Verilog] proje2

Description: it is code for implement the FIFO in VHDL. FIFO is first in first out memory.
Platform: | Size: 1024 | Author: Arash | Hits:

[VHDL-FPGA-Verilog] VHDL-8bitFIFO

Description: FIFO的宽度：也就是英文资料里常看到的THE WIDTH，它只的是FIFO一次读写操作的数据位，就像MCU有8位和16位，ARM 32位等等，本程序实现8位的FIFO功能,三位格雷码可表示8位的深度。-THE WIDTH of THE FIFO: namely information in English often see THE WIDTH, it is only a FIFO data read and write operations, as has 8 bit or 16 bit MCU, ARM 32-bit, etc., THE program achieve THE function of eight FIFO, three gray code can be expressed THE depth of THE eight.
Platform: | Size: 1024 | Author: 刘伟 | Hits:

[VHDL-FPGA-Verilog] code

Description: 本源码是基于VHDL语言环境下的基础实验源码，共分七个部分。分别是：序列检测器、数字密码锁、四位有符号数除法、同步FIFO、DPLL的设计以及Cordic 算法实现。对于VHDL的初学者具有极大的参考价值。-The source is based on experimental basis source VHDL language environment, it is divided into seven sections. They are: the sequence detector, digital locks, four have signed division synchronous FIFO, DPLL design and Cordic algorithm. For beginners VHDL great reference value.
Platform: | Size: 20480 | Author: 朱召宇 | Hits:

[Other] FIFO_TXD

Description: fifo标准协议接受代码，基于fpga，vhdl语言-fifo standard protocol accepted code, based on fpga, vhdl language
Platform: | Size: 2048 | Author: 宋晨 | Hits:

[VHDL-FPGA-Verilog] VHDL_RAM_FIFO_ROM

Description: VHDL代码实现FIFO从ROM中读取数据然后传输到RAM中-VHDL code for FIFO read data ROM to RAM and then transfer
Platform: | Size: 9634816 | Author: 胡小军 | Hits:

[Other] FIFO

Description: FIFO code implemented in VHDL. FIFO is nothing but first in first out data buffer Here i have implement it in VHDL
Platform: | Size: 67584 | Author: sam | Hits:

[VHDL-FPGA-Verilog] uart_design

Description: UART设计的VERILOG代码，具有FIFO功能，能实现CPU与外设之间的数据与指令通信(The VERILOG code designed by UART, which has the function of FIFO, can realize the communication between the data and the instruction between the CPU and the peripherals)
Platform: | Size: 547840 | Author: 沐羽1996 | Hits:
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